Document Type : Original Manuscript
Department of Computer, Bam Branch, Islamic Azad University, Bam, Iran
Department of Computer Engineering, Kerman Branch, Islamic Azad University, Kerman, Iran
In this paper, a full adder cell based on a parallel design using MOSFET technology is presented. The main goal of designing this full adder cell is to reduce critical path delay in adder circuits. The proposed design by reduces length of data path and positively, affects speed and power consumption parameters. In order to evaluate the proposed full adder cell, several simulations are performed in different load capacitors, frequencies and temperatures using HSPICE in 32nm CMOS technologies. The proposed full adder cells were compared with eight other full adder cells using 4-bit Ripple Carry Adder (RCA) and 8-bit RCA circuits in power consumption, speed, and Power Delay Product (PDP) parameters. The obtained results indicate that the proposed design is faster than other designs due to
a shortened data path. The results of the simulations confirm the higher efficiency of the proposed full adder cell with respect to other designs.