Presenting a Fault Tolerant Mechanism for Buffering Fault in Network on Chips

Authors

1 Department of Computer Engineering Arak Branch, Islamic Azad University, Arak, Iran

2 Professor, Department of Electronic Engineering, Tehran University, Tehran, Iran

Abstract

As technology scales deep into the nanometer regime, on-chip communication becomes more susceptible to transient noise sources, such as crosstalk, external radiation, and spurious voltage spikes. The Network on chip s modularity and reusability has brought about the use of error control methods to address transient errors in Network on chip links.In this work, we design a fault tolerance router with efficient area and power dissipated. Actually, we exploit the free virtual channel to store the redundant data. Virtual channel is used for deadlock avoidance it can be implement as 2, 4 or 8 channel. The almost time we can find a free channel that we can use in fault tolerance mechanism. We describe the proposed architecture with VHDL and implemented with synopsis compiler design. We use analytical model to evaluate the fault tolerance. The result shows that we improve the dynamic power dissipation, area, and reliability.

Keywords